1. Field of the Invention
The present invention relates to a chip package structure and a chip packaging process. More particularly, the present invention relates to a warp-resistant chip package structure and chip packaging process for improving the yield of production.
2. Description of the Related Art
With the rapid progress in electronic technologies and semiconductor manufacturing in recent years, a lot of personalized and multifunctional electronic products flooded the market. Moreover, these electronic products are often miniaturized and downsized for portability. In the area of semiconductor production, the fabrication of integrated circuits (IC) can be roughly divided into three main stages: integrated circuit design, integrated circuit fabrication and integrated circuit packaging. In general, raw chips are produced after going through a series of steps including wafer production, circuit design, mask production and wafer dicing operation. Each piece of raw chip cut out from the wafer must be electrically connected to a substrate for external communication through the bonding pads thereon. Moreover, each raw chip must be encapsulated by an encapsulant to form an IC package that prevents moisture, heat or electrical noise from interfering with its function and a medium for connecting with an external circuit such as a printed circuit board (PCB) or other packaging substrate.
Due to the rapid advance in IC production technologies, the operating speed of each chip continues to increase so that various types of digital data processing and computation are increasingly efficient. However, as the level of integration of circuits within each chip increases exponentially, the amount of heat generated per unit area in normal operation also increases accordingly. At maximum operating speed, the need to dissipate the heat away from the chip fast enough is critical. Conventionally, a metallic heat sink with high heat-dissipating capacity is disposed on a chip package to absorb heat and conduct the heat away to the surrounding atmosphere.
FIG. 1 is a schematic cross-sectional view showing the structure of a conventional chip package. As shown in FIG. 1, the chip package structure 100 comprises a chip 110, a circuit substrate 120, a heat sink 130 and an encapsulant 140. The circuit substrate 120 having an opening 120a therein is disposed on the heat sink 130. The back surface 110b of the chip 110 is mounted to the heat sink 130 within the opening 120a of the circuit substrate 120 by adhesive glue (not shown). The active surface 110a of the chip 110 has a plurality of bonding pads 112 thereon. The circuit substrate 120 has a plurality of first bonding pads 122a and a plurality of second bonding pads 122b surrounding the first bonding pads 122a. The chip 110 and the circuit board 120 are electrically connected through a wire-bonding process. Typically, each bonding pad 112 on the chip 110 is electrically connected to a corresponding first bonding pad 122a on the circuit substrate 120 through a conductive wire 150.
As shown in FIG. 1, the encapsulant 140 fills up the opening 120a entirely and encapsulates the chip 110, the conductive wires 150 and the first bonding pads 122a on the circuit substrate 120. The encapsulant 140 prevents moisture, heat or electrical noise from affecting the chip 110 and protects the conductive wires 150 against mechanical damage. Furthermore, a plurality of conductive bumps 160 is formed on the second bonding pads 122b of the circuit substrate 120 to serve as a medium of contact for connecting the chip package 100 to external circuits.
To form the encapsulant in the aforementioned chip packaging process, a molding compound such as epoxy resin is heated to a semi-liquid form at a high temperature and injected into a mold. Thereafter, the molding compound is cooled to form a solidified encapsulant. However, the heat sink and the encapsulant have different coefficient of thermal expansion (CTE). Thus, a thermal stress of non-uniform magnitude is often generated inside the chip package somewhere between the heat sink and the encapsulant during the cooling process. Due to the thermal stress, the chip package is more likely to warp or crack. The warping or cracking of the chip package frequently leads to irreversible damage to either the chip or the conductive wires. Therefore, the yield of the chip packaging process can not be enhanced effectively.